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A Guide to The "New" AMD Socket A
Athlon Processor

Last updated: 6/11/00

The Athlon has a high performance memory Cache' architecture.  L1 cache, closest the CPU innards is comprised of two separate 64 KByte caches, one each for data and instructions.  The next layer of cache', L2, is 256 KBytes of on-die cache'.  The L2 cache' is 16-way associative.  The "Classic" Athlon had 2-way associative cache'.  I quote the AMD experts:

"Higher associativity dramatically improves application performance since more local application data resides in the high-speed L2 cache memory instead of system memory. Finally, the integrated L2 cache tags improves performance by quickly indicating whether critical application data is located within the L2 cache."

In short, the "New" Athlon has 128 Kbytes of L1 cache' and 256 KBytes of on-die L2 cache'.  The L2 cache' runs at the same speed as the processor unit.

The Athlon has a 200 Mhz System bus.  The block diagram to the right shows the Athlon with AMD's 750 chipset (I plan to write-up VIA's KT133 chipset before long) consisting of the 751 Northbridge System Controller and 756 Southbridge Peripheral bus controller.  Remember, the cache' is inside the CPU.  The System Bus goes between the processor and the Northbridge.  The Northbridge interfaces to the three additional buses: the memory bus to main memory (100 Mhz, PC-100), the AGP bus going to the AGP graphics slot (66 Mhz, AGP 2X), and the PCI bus (33 Mhz).  The Southbridge hangs off the PCI bus.  The System Bus or Front Side Bus (FSB) is the data expressway or funnel which carries all of the data to and from the CPU from the other buses via the Northbridge.  The System Bus consists of three independent, synchronously-clocked 200 Mhz high-speed channels:

  • 13-pin processor request channel

  • 13-pin system probe channel

  • 72-pin data transfer channel (8-bit ECC)

The bus is capable of transferring peak data rates of  1.6 Bytes per second and 64-Bytre Burst data transfers.  In short, the Athlon has a 200 Mhz System Bus between it and the Northbridge chip.

The "New" Athlon uses a Socket A.  There is a  Slot A version of the Thunderbird with off-die L2 cache,' but it is an OEM (Original Equipment Manufacturer version) and will not be generally available through retail channels.


  • The "New" Athlon is the second seventh generation X86 processor.

  • X86 instructions are decoded into Athlon instructions.

  • The Instruction Control Unit is a managed buffer between the decoders and schedulers.

  • Two execution schedulers manage the execution pipelines.

  • There are nine independent execution pipelines.  Three of them are floating point units.

  • The Athlon implements Enhanced 3DNow!™ with SMID.

  • The Athlon has advanced branch prediction logic

  • 128 Kbytes of L1 cache' and 256 KBytes of full-speed, on-die L2 cache.'

  • There is a 200 Mhz System Bus between the CPU and the Northbridge chip.

  • The "New" Athlon uses a Socket A motherboard.


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